1. Field of the Invention
The present invention relates to phase-lock loops, and in particular, to phase-lock loops with presettable phase detectors.
2. Description of the Related Art
In communication systems, such as those operating in a time division duplex (TDD) or time division multiple access (TDMA) mode, a phase-lock loop (PLL) is often used to provide the modulated radio frequency (RF) signal. In such systems, the PLL may be modulated directly, i.e. where the loop is closed to acquire phase and/or frequency locking and the loop is opened during modulation. Benefits of such a modulation technique include fast acquisition and low spurious signals by the PLL.
However, a problem encountered when re-closing the loop involves the phase, or frequency, settling time needed to re-acquire phase-lock. In direct, or open-loop, modulation of a PLL the loop is opened while the modulation signal is applied directly to the PLL's voltage-controlled oscillator (VCO). While the loop is opened, the phase detector, i.e. the dividers (e.g. counters) and phase comparator, loses all information about any phase difference(s) between the reference signal and the feedback signal from the VCO. Upon re-closing the loop after modulation, the feedback-reference phase difference is unknown. Accordingly, the PLL will try to lock initially to a random phase, which can cause a big jump in frequency. This in turn translates to a large phase-settling time interval which is often longer than the settling time following a frequency step made while the loop remains locked, and which can be problematic in systems such as wireless local area network (LAN) systems where the transceiver needs to be able to receive immediately after transmitting a packet of data.
Hence, it would be desireable to have a PLL for which the phase-settling time after the loop is re-closed following direct modulation thereof can be preselected or minimized.